Chapter 2. Cray X1 Instruction Set Overview

Table of Contents
2.1. Data Types
2.2. Registers
2.3. CAL Source Statement Format
2.4. Scalar Instructions
2.5. Vector Instructions
2.6. Memory Ordering
2.7. Summary of Rules
2.8. Special Syntax Forms

This chapter gives an overview of the Cray X1 system instruction set. The Cray X1 system is an implementation of the Cray NV-1 instruction set architecture. The full instruction set is listed in Chapter 7 and is described in detail in the System Programmer Reference for Cray X1 Systems.

2.1. Data Types

The Cray X1 system has four fundamental data types:

The default for the data type of an instruction is L. The other data types are usually specified in assembly language notation with a suffix on the result register.

An instruction's type is usually the type of its result. For comparisons, however, the instruction's type is the type of its operands.

The result of a scalar comparison is a Boolean truth value (0 or 1) of type L, and the result of a vector comparison is a vector of Boolean truth values in a mask register.

In addition, some instructions reference 8-bit quantities (Bytes) and 16-bit quantities (Halfwords).

The convention used for numbering bits in a data type is that bit 2n is referred to as bit n. In a range of bits within a data type from 2n to 2m where 2n is a higher order bit than 2m, the bits are specified as n:m.

2.1.1. Integer

The Word type W comprises 32-bit twos complement signed integers in the range

-2147483648 ... 2147483647
-0x80000000 ... 0x7fffffff

The Longword type L comprises 64-bit twos complement signed integers in the range

-9223372036854775808 ... 9223372036854775807
-0x8000000000000000  ... 0x7fffffffffffffff

Interpretations of these types as C unsigned integers mod 232 and 264 are supported in comparisons and implicitly in the hi(j*k) multiplication function. The assembly language syntax uses the notations UW and UL for unsigned comparisons.

Special instructions accelerate loads and stores of 8-bit and 16-bit integers from 64-bit Longword containers.

2.1.2. Floating-point

The Cray X1 system conforms to the IEEE-754 standard for floating-point arithmetic with the exception of subnormal numbers.

The 32-bit single precision floating-point type S has this format:








Mantissa (implicit normalization)

The 64-bit double precision floating-point type D has this format:








Mantissa (implicit normalization)

A 128-bit floating-point format is implemented by software. It comprises a standard 64-bit D value with 64 additional mantissa bits.

2.1.3. Addresses

Memory is addressed for instruction fetches, address and scalar register loads and stores, vector loads and stores, and atomic memory operations. All addresses have the same format and interpretation. They are 64-bit values that identify a byte offset in a virtual address space.

Addresses must be strongly aligned except for the special unaligned (,ua) load and store instructions. This means that instruction fetches and other 32-bit references must have zero bits in the lowest order two bit positions and that 64-bit references must have three lowest order zero bits.

The highest order bit positions (63:48) of a user virtual address must be zero. Distributed memory applications use bits 47:38 of the virtual address for a logical node number.

Data caches are always coherent, but the instruction caches are not. Self-modifying code must synchronize the instruction cache with an explicit lsync,i instruction.

The Cray X1 system addresses memory in big-endian order. If a 64-bit Longword is stored at aligned address x, a 32-bit load from x+0 will retrieve its upper order 32 bits and a 32-bit load from x+4 will retrieve its lower order 32 bits.